exercise 1 - pre-final

memory allocation is the allocation of memory storage for use in a computer program during the runtime of that program. It is a way of distributing ownership of limited memory resources among many pieces of data and code. Importantly, the amount of memory allocated is determined by the program at the time of allocation and need not be known in advance. A dynamic allocation exists until it is explicitly released, either by the programmer or by a garbage collector; this is notably different from automatic and static memory allocation, which require advance knowledge of the required amount of memory and have a fixed duration. It is said that an object so allocated has dynamic lifetime.
Segmentation is one of the most common ways to achieve memory protection; another common one is paging. Segmentation means that a part or parts of the memory will be sealed off from the currently running process, through the use of hardware registers. If the data that is about to be read or written to is outside the permitted address space of that process, a segmentation fault will result.
This usage should not be confused with that of the memory segments used by early x86 processor architectures.
For details of x86's implementation of segmentation in both 16-bit and 32-bit mode, please see the article on memory segments.
Segmentation is a memory-management scheme that supports this user view of memory. A logical address space is actually a collection of segments. Each segment has a name and a length. The address specifies both the segment name and the offset within the segment. The user therefore specifies each address by 2 parameters: a segment name and an offset.
Input / Output ports are Ports located on the outside of a computer that allows for an input or output device to be connected to it.

Internal registers - The AVR is a Harvard architecture 8-bit RISC single chip microcontroller (µC) which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to One-Time Programmable ROM, EPROM, or EEPROM used by other microcontrollers at the time.

An interrupt vector is the memory address of an interrupt handler, or an index into an array called an interrupt vector table or dispatch table. Interrupt vector tables contain the memory addresses of interrupt handlers. When an interrupt is generated, the processor saves its execution state via a context switch, and begins execution of the interrupt handler at the interrupt vector
BIOS (pronounced [ˈbaɪoʊs]), in computing, stands for Basic Input/Output System.[1] [2]
The term is incorrectly known as Binary Input/Output System, Basic Integrated Operating System and occasionally Built In Operating System for example in Neal Stephenson's novel Snow Crash[1].
BIOS refers to the firmware code run by an IBM compatible PC when first powered on. The primary function of the BIOS is to prepare the machine so other software programs stored on various media (such as hard drives, floppies, and CDs) can load, execute, and assume control of the PC[3]. This process is known as booting up.
BIOS can also be said to be a coded program embedded on a chip that recognizes and controls various devices that make up the PC. The term BIOS is specific to personal computer vendors. Among other classes of computers, the generic terms boot monitor, boot loader or boot ROM are commonly used. Boot is short for bootstrapping.
The term first appeared in the CP/M operating system, describing the part of CP/M loaded during boot time that interfaced directly with the hardware (CP/M machines usually had a simple boot loader in ROM, and nothing else). Most versions of DOS have a file called "IBMBIO.COM" or "IO.SYS" that is analogous to the CP/M disk BIOS.

DOS (from Disk Operating System) commonly refers to the family of closely related operating systems which dominated the IBM PC compatible market between 1981 and 1995 (or until about 2000, if Windows 9x systems are included): DR-DOS, FreeDOS, MS-DOS, Novell-DOS, OpenDOS, PC-DOS, PTS-DOS, ROM-DOS and several others. They are single user, single task systems. MS-DOS from Microsoft was the most widely used. These operating systems ran on IBM PC type hardware using the Intel x86 CPUs or their compatible cousins from other makers. MS-DOS, inspired by CP/M, is still common today and was the foundation for many of Microsoft's operating systems (from Windows 1.0 through Windows Me). MS-DOS was later abandoned as the foundation for their operating systems.


An instruction set is (a list of) all instructions, and all their variations, that a processor can execute.
Instructions include:
arithmetic such as add and subtract
logic instructions such as and, or, and not
data instructions such as move, input, output, load, and store
control flow instructions such as goto, if ... goto, call, and return.
An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O. An ISA includes a specification of the set of opcodes (machine language), the native commands implemented by a particular CPU design.
Instruction set architecture is distinguished from the microarchitecture, which is the set of processor design techniques used to implement the instruction set. Computers with different microarchitectures can share a common instruction set. For example, the Intel Pentium and the AMD Athlon implement nearly identical versions of the x86 instruction set, but have radically different internal designs.
This concept can be extended to unique ISAs like TIMI (Technology-Independent Machine Interface) present in the IBM System/38 and IBM AS/400. TIMI is an ISA that is implemented as low-level software and functionally resembles what is now referred to as a virtual machine. It was designed to increase the longevity of the platform and applications written for it, allowing the entire platform to be moved to very different hardware without having to modify any software except that which comprises TIMI itself. This allowed IBM to move the AS/400 platform from an older CISC architecture to the newer POWER architecture without having to rewrite any parts of the OS or software associated with it.

Data transfer instructions
Move
mov src, dest
GAS Syntax
mov dest, src
Intel syntax
Move
The mov instruction copies the src operand in the dest operand.
Operands
src
Immediate
Register
Memory
dest
Register
Memory
Modified flags
No FLAGS are modified by this instruction
Example.data value: .long 2 .text .global _start _start: movl $6, %eax # %eax is now 6 movw %eax, value # value is now 6 movl 0, %ebx # %ebx is now 0 movb %al, %bl # %ebx is now 6 movl value, %ebx # %ebx is now 2 movl $value, %esi # %esi is now the address of value movw value(, %ebx, 1), %bx # %ebx is now 0 # Linux sys_exit mov $1, %eax xorl %ebx, %ebx int $0x80
Data Swap
xchg src, dest
GAS Syntax
xchg dest, src
Intel syntax
Exchange
The xchg instruction swaps the src operand with the dest operand.
Operands
src
Register
Memory
dest
Register
Memory
Modified flags
No FLAGS are modified by this instruction
Example.data value: .long 2 .text .global _start _start: movl $54, %ebx xchgl value, %ebx # %ebx is now 2 # value is now 54 xchgw %ax, value # Value is now 0 # %eax is now 54 xchgb %al, %bl # %ebx is now 54 # %eax is now 2 xchgw value(%eax), %aw # value is now 0x00020000 = 131072 # %eax is now 0 # Linux sys_exit mov $1, %eax xorl %ebx, %ebx int $0x80
Move and Extend
movz src, dest
GAS Syntax
movz dest, src
Intel syntax
Move zero extend
The movz instruction copies the src operand in the dest operand and pads the remaining bits not provided by src with zeros (0).
This instruction is useful for copying an unsigned small value to a bigger register.
Operands
src
Immediate
Register
Memory
dest
Register
Memory
Modified flags
No FLAGS are modified by this instruction
Example.data value: .long 34000byteval: .byte 204 .text .global _start _start: movzbw byteval, %ax # %eax is now 204 movzwl %ax, value # value is now 204 movzbl byteval, %esi # %esi is now 204 # Linux sys_exit mov $1, %eax xorl %ebx, %ebx int $0x80
movs src, dest
GAS Syntax
movs dest, src
Intel syntax
Move sign extend.
The movs instruction copies the src operand in the dest operand and pads the remaining bits not provided by src the sign of src.
This instruction is useful for copying a signed small value to a bigger register.
Operands
src
Immediate
Register
Memory
dest
Register
Memory
Modified flags
No FLAGS are modified by this instruction
Example.data value: .long 34000byteval: .byte -204 .text .global _start _start: movsbw byteval, %ax # %eax is now -204 movswl %ax, value # value is now -204 movsbl byteval, %esi # %esi is now -204 # Linux sys_exit mov $1, %eax xorl %ebx, %ebx int $0x80
Move by Data Size
movsb
Move byte
The movsb instruction copies one byte from the location specified in esi to the location specified in edi.
Operands
None.
Modified flags
No FLAGS are modified by this instruction
Examplesection .code; copy mystr into mystr2mov esi, mystrmov edi, mystr2cldrep movsb section .bssmystr2: resb 6 section .datamystr db "Hello", 0x0
movsw
Move word
The movsw instruction copies one word (two bytes) from the location specified in esi to the location specified in edi.
Operands
None.
Modified flags
No FLAGS are modified by this instruction
Examplesection .code; copy mystr into mystr2mov esi, mystrmov edi, mystr2cldrep movsw; due to endianess, the resulting mystr2 would be aAbBcC\0a section .bssmystr2: resb 8 section .datamystr db "AaBbCca", 0x0

Branch instruction
A branch (or jump on some computer architectures, such as the PDP-8 and Intel x86) is a point in a computer program where the flow of control is altered. The term branch is usually used when referring to a program written in machine code or assembly language; in a high-level programming language, branches usually take the form of conditional statements, subroutine calls or GOTO statements. An instruction that causes a branch, a branch instruction, can be taken or not taken: if a branch is not taken, the flow of control is unchanged and the next instruction to be executed is the instruction immediately following the current instruction in memory; if taken, the next instruction to be executed is an instruction at some other place in memory. There are two usual forms of branch instruction: a conditional branch that can be either taken or not taken, depending on a condition such as a CPU flag, and an unconditional branch which is always taken.
Conditional Branch
(computer science) A computer instruction that will cause the proper one of two or more addresses to be used in obtaining the next instruction, depending on some property of a numerical expression that may be the result of some previous instruction. Also known as conditional branch; conditional transfer; decision instruction; discrimination; IF statement.
unconditional jump
(computer science) A digital-computer instruction that interrupts the normal process of obtaining instructions in an ordered sequence, and specifies the address from which the next instruction must be taken. Also known as unconditional transfer.

Every microprocessor has an instruction set which can perform a series of instructions (called using assembly commands). Arithmetic instructions are the subcategory of instructions that perform arithmetic operations (addition, subtraction, you know, that shit we learnt in elementary school) and also, logical operations (the heart and soul of every electronic device). Arithmetic operations are in general easily understood, but it must be mentioned that there are only two operands involved in every such operation and the result is always stored in one of the two operands. Thus, your typical addition as seen in any common programming language does not look like a=b+c but has the nature of the imperative statement:
Add A to B or rather: Add contents-of-first-register to contents-of-second-registerwhich in turn, leads to the conclusion that adding two numbers will always overwrite one of them in order to store the result. In standard Intel assembly language, arithmetic and logical operations have a syntax similar to this:add reg1,reg2which means "add reg2 to reg1"; oh never uses symbols like +-*/, etc. as in mathematics. These symbols have other uses, more important uses.
LOOPING INSTRUCTIONS
1. A method of processing loop instructions using a data processing device having a central processing unit (CPU) and a coprocessor, wherein the CPU fetches and predecodes instructions retrieved from program memory and determines whether the instructions are CPU-type or coprocessor-type, comprising the steps of: decoding the coprocessor-type instructions by the coprocessor and if a loop operation is decoded, retrieving from the program memory the instructions within the loop; storing the retrieved instructions within the loop in a loop buffer: executing at least one coprocessor-type instruction from the loop buffer by the coprocessor, and forwarding any CPU-type instructions from the loop buffer to the CPU for execution ; and inhibiting instruction fetch from the program memory while instructions within the loop are executed in a subsequent iteration of the loop.
2. The method of claim 1, further including the step of accessing the instructions within the loop from the loop buffer in a subsequent iteration of the loop. 3. The method of claim 1, further including determining a backward branch distance for use by the CPU to control branching to and from the loop. 4. The method of claim 1 further including the steps of: determining from the loop instruction a number of iterations of the loop operation; decrementing by the coprocessor the number of iterations upon completion of each loop; and signaling to the CPU the completion of the loop operation when reaching the end of the number of iterations. 5. The method of claim 1, wherein said storing step includes storing 'n' loop instructions in 'm' registers of the loop buffer and addressing the 'm' registers by log2m in least significant bits (LSBs) of a program counter which is also used for addressing the program memory, wherein n or m is any natural number and n is less than or equal to m. 6. The method of claim 5, further including the steps of accessing the instructions stored in the loop buffer through a multiplexer and controlling the multiplexer output by the log2m LSBs of the program counter. 7. The method of claim 5, wherein a first instruction within the loop is stored in one of the m registers addressed by the LSBs of the program counter. 8. The method of claim 1, further including the steps of signaling the presence or absence of an active loop instruction by a loop buffer flag in each of the 'm' registers in the loop buffer, the presence of an active instruction in a register is indicated by a preassigned signal in the loop buffer flag. 9. The method of claim 8, further including the step of accessing each flag in the loop buffer by log2m least significant bits of a program counter used for addressing the program memory. 10. The method of claim 8, further including the step of multiplexing an instruction from the loop buffer and the program memory, the multiplexing is dependent upon a presence of an active instruction signal from a loop buffer flag. 11. The method of claim 8, wherein said step of inhibiting instruction fetch from the program memory includes sending an inhibit signal to the program memory when the preassigned signal in the loop buffer flag is read and indicates the presence of an active loop instruction. 12. The method of claim 11, wherein the preassigned signal in each of said loop buffers is selectively alterable by the CPU independent of the presence or absence of an active instruction in corresponding registers. 13. The method of claim 8, further including the step of clearing the loop buffer flag when the loop operation is completed. 14. A data processing device comprising: a central processing unit (CPU) for fetching instructions from a program memory, predecoding the instructions and sending a signal (CCLK) to a coprocessor if a coprocessor-type instruction is decoded; a coprocessor for decoding the coprocessor-type instructions upon receipt of the signal (CCLK); and a loop buffer for receiving from the program memory instructions within a loop and storing the instructions within the loop when the coprocessor decodes a loop operation from the coprocessor-type instructions, wherein the instructions within the loop are retrieved from the loop buffer for execution in a subsequent iteration of the loop, and wherein the loop buffer instructions of coprocessor-type are executed by the coprocessor and the loop buffer instructions of CPU-type are forwarded to the CPU for execution. 15. The device of claim 14, wherein a disable signal is sent to the program memory for inhibiting access of the program memory while the instructions within the loop are retrieved from the loop buffer. 16. The device of claim 14, wherein the loop buffer includes 'm' registers, each having a corresponding loop buffer flag for indicating whether the corresponding register is filled with an instruction. 17. The device of claim 16, wherein the loop buffer flags are accessed by log2m least significant bits of a program counter used for addressing the program memory. 18. The device of claim 16, wherein a program memory inhibit signal is generated based on a signal read from the loop buffer flag. 19. The device of claim 14, wherein the loop buffer includes 'm' registers and the registers are addressed by log2m LSBs of a program counter used for addressing the program memory. 20. The device of claim 16, further including a multiplexer for multiplexing between the instructions retrieved from the program memory and the instructions retrieved from the loop buffer, the multiplexor being controlled by signals read from the loop buffer flags. 21. The device of claim 14, wherein the coprocessor decodes from a loop instruction a loop block size and a number of iterations of looping, and calculates a backward branch distance for use by the CPU to control branching to and from the loop. 22. The device of claim 21, wherein the backward branch distance is the loop block size minus one. 23. A data processing device comprising: a central processing unit (CPU) for fetching instructions from a program memory, predecoding the instructions and sending a signal (CCLK) to a coprocessor if a coprocessor-type instruction is decoded; a coprocessor for decoding the coprocessor-type instructions upon receipt of the signal (CCLK); and a loop buffer for receiving from the program memory instructions within a loop and storing the instructions within the loop when the coprocessor decodes a loop operation from the coprocessor-type instructions, wherein the instructions within the loop are retrieved from the loop buffer for execution in a subsequent iteration of the loop, wherein the loop buffer instructions of coprocessor-type are executed by the coprocessor and the loop buffer instructions of CPU-type are forwarded to the CPU for execution, and wherein a disable signal is sent to the program memory for inhibiting access of the program memory while the instructions within the loop are retrieved from the loop buffer.